1. Field of the Invention
The present invention relates to a method of semiconductor patterning. More particularly, the present invention relates to a method of simultaneously forming patterns on a die of an alignment mark and other dies.
2. Description of the Related Art
Photolithography is a critical process that decides whether or not a semiconductor device can be successfully fabricated. Thus, photography occupies an important position in the semiconductor fabrication process. A common device fabrication process is taken as an example. Usually, according to the complexity of a device, a fabrication process needs 10 to 18 photolithography and exposure steps. In order to precisely transfer the pattern onto the chip, an alignment between layers needs to be performed before each photoresist exposure step. This is in order to avoid incorrect pattern transfer and the consequent chip disposal.
In a traditional exposure process, alignment mark is formed over the chip according to the location of a mask in order to achieve alignment. In order to avoid damage on the alignment mask during semiconductor fabrication, usually no pattern is formed around the alignment mark. However, this causes the oxide layer formed over the empty region around the alignment mark to remain to form a residual oxide layer after performance of chemical mechanical processing.
A fabrication process of a shallow trench isolation is taken as an example. FIGS. 1A through 1C are schematic cross-sectional views showing the progression of steps for producing a conventional shallow trench isolation structure.
As shown in FIG. 1A, a substrate 100 having alignment marks 102 thereon is provided. A mask layer 104 is formed over the substrate 100, and then a photoresist layer 106 is formed over the mask layer 104. Using the mask layer 104 as an etching mask, the mask layer 104 and a portion of the substrate 100 are removed to form a trench 108 in the substrate 100.
As shown in FIG. 1B, the photoresist layer 106 is removed and then a silicon oxide layer 110 is formed over the substrate 100 so that the mask layer 104 is covered while the trench 108 is filled.
As shown in FIG. 1C, a chemical-mechanical polishing operation is carried out to remove redundant silicon oxide material from the silicon oxide layer 110 using the mask layer 104 as a polishing stop layer. Subsequently, a silicon oxide layer 110a is formed inside the trench 108. Lastly, the mask layer 104 is removed.
In general, the density of trenches on a silicon chip is non-uniform and there are some empty regions on the silicon chip free of isolation structures. In the process of removing the oxide material above the mask layer 104 in a chemical-mechanical polishing operation, some of the oxide material above the empty region 112 will be retained to form a residual oxide layer 110b. 
To reduce thickness of the residual oxide film on top of empty regions, dummy isolation regions are sometimes formed over the empty regions 112 on the substrate 100 so that a uniform polish can be achieved. FIGS. 2A through 2D are schematic cross-sectional views showing the progression of steps for producing conventional shallow trench isolation structures and dummy isolation regions on empty regions in a substrate.
As shown in FIG. 2A, a photomask having both isolation region pattern 114 and dummy isolation region pattern 116 are used to pattern a photoresist layer 106. After photo-exposure, the patterns are transferred to the photoresist layer 106.
As shown in FIG. 2B, the photoresist layer 106 is developed. Hence, the isolation region pattern 114 and the dummy isolation region 116 are formed in the photoresist layer 106. Using the photoresist layer 106 as an etching mask, the mask layer 104 and the substrate 100 are etched to form trenches 108 in the isolation region as well as dummy trenches 118 in the dummy isolation region.
As shown in FIG. 2C, the photoresist layer 106 is removed and then an oxide layer 110 is formed over the substrate 100. Hence, the mask layer 104 is covered while the trenches 108 and the dummy trenches 118 are filled.
As shown in FIG. 2D, a chemical-mechanical polishing operation is carried out to remove any redundant oxide material above the mask layer 104. The mask layer 104 is also removed to form isolation structures 110a and dummy isolation structures 110c in the substrate 100.
In the aforementioned method, the isolation region pattern 114 and the dummy isolation pattern 116 are formed on the same photoresist layer 106 as shown in FIG. 2A. In carrying out photo-exposure, a pattern on the photomask 400 in FIG. 4 is transferred to each exposure shot 120 in the silicon chip 100 shown in FIG. 3 one by one to form isolation region pattern 114 in the photoresist layer 106 above the substrate (silicon chip) 100. Thereafter, the pattern of the photomask 400 is transferred onto the empty regions 112 around the alignment mark 102. In this manner, the isolation region pattern 114 and the dummy isolation pattern 116 are formed on the same photoresist layer 106.
As shown in FIG. 3, dimensions of shots 122 of the alignment marks 102 above the silicon chip are different from a dimension of the exposure shots 120 in each exposure operation. During an exposure process of dummy isolation region pattern, a corner 404 (for example, the left/upper corner) of the chromium film 402 on the photomask 400 in FIG. 4 is aligned with a corner 130 (for example, the upper/left corner) of an alignment shot 122. In addition, the non-transparent blade 300 of a stepper is used to block a portion of the area on the photomask 400 that corresponds to the alignment mark 102 and a portion of the alignment marking shot 122. Because of the chromium film 402 on the photomask 400 and the non-transparent blade 300 of the stepper, light is permitted to pass in a specified region only. Consequently, trench pattern at the corner 404 of the photomask 400 is transferred to the corner 130 of shot 122 only. To form a complete dummy isolation pattern 116, the photoresist layer 106 at the other corners of the alignment shot 122 must be transferred by carrying out similar steps.
The method demands a multiple of exposures to form a complete dummy isolation pattern 116 in the photoresist layer 106 above the alignment shot 122. Consequently, throughput of the station decreases and wear of the non-transparent blades increases.
In general, the number of exposures can be reduced by placing the alignment mark to one side of the alignment shot rather than the middle and attaching neighboring alignment shots shot-to-shot as shown in the magnified view of FIG. 3. However, by so doing, the chip areas surrounding such alignment marks are likely to be affected by subsequent polishing operations.
The invention is directed to a method of a forming semiconductor pattern. The method includes dividing a chip into a plurality of first exposure shots and a plurality of second exposure shots. After an alignment mark is formed in one of the dies of a first exposure shot, a waiting-for-patterning layer is formed over the chip. A negative photoresist layer is formed over the waiting-for-patterning layer. First exposure processes are carried out one-by-one to form a plurality of first exposed regions and a plurality of unexposed regions in the negative photoresist above the first exposure shots and the second exposure shots. A second exposure process is next carried out to form a second exposed region in the negative photoresist above the alignment mark. The second exposed region overlaps with the first exposed region and the unexposed region above the self-aligned mark and the overlapping region covers the alignment mark region. A photoresist development is carried out to remove the negative photoresist in the unexposed regions and expose the waiting-for-patterning layer. Using the negative photoresist layer as a mask, the exposed waiting-for-patterning layer is etched to form a pattern. The negative photoresist layer is removed.
This invention also provides a method of forming semiconductor patterns. A substrate having a plurality of dies thereon is provided. The substrate is divided into a plurality of first exposure shots and a plurality of second exposure shots. An alignment mark is formed in one of the dies of a first exposure shot. A mask layer is formed over the substrate and then a negative photoresist layer is formed over the mask layer. First exposure processes are carried out one-by-one to form a plurality of first exposed regions and a plurality of unexposed regions in the negative photoresist layer above the first exposure shots and the second exposure shots individually. The unexposed regions include a plurality of trench pattern. A second exposure process is next carried out to form a second exposed region in the negative photoresist above the alignment mark. The second exposed region overlaps with the first exposed region and the unexposed region above the alignment mark, and the overlapping region covers the alignment mark region. A photoresist development is carried out to remove the negative photoresist in the unexposed regions and expose the mask layer. Using the negative photoresist layer as a mask, the exposed mask layer is removed to form a trench pattern. The negative photoresist layer is removed. Using the patterned mask layer as a mask, a portion of the substrate is removed to form a plurality of trenches in the dies amongst the first exposure shots and the second exposure shots. An insulation layer is formed over the chip to cover the mask layer and fill the trenches. A chemical-mechanical polishing operation is carried out to remove the excess insulating material above the mask layer. The mask layer is removed so that the insulation layer inside each trench of the second exposure shots becomes an isolation region. The insulation layer inside each trench of the second exposure shots becomes a dummy isolation region.
According to the embodiment of this invention, dimensions of the first exposure shots containing the alignment mark are identical to other second exposure shots. Hence, when the aforementioned exposure operation is conducted, the desired pattern of the first exposure shot containing the alignment will emerge as long as the stepper carries out the exposure sequentially. In other words, one exposure needs to be carried out to form the first exposure shot that contains the alignment mark. Compared with the conventional multi-step exposure process, the method of this invention is faster. In addition, this invention is also capable of increasing throughput, reducing non-transparent blade wear and lowering production cost.
In addition, by forming a negative photoresist layer over the substrate, chromium film on photomask for clearing peripheral region can be used to align with the periphery of the alignment mark region. Hence, light can pass through the clearing region and transfer the pattern to the chip so that an exposed region is formed above the alignment mark. Because position and dimensions of the exposed region depend on the chromium blocking layer in the photomask rather than the mask-blocking non-transparent blade in a stepper, optical diffraction can be prevented. Therefore, the pattern on the clearing region of the photomask can be correctly transferred to the photoresist layer.
In this invention, dummy isolation regions are formed around the peripheral region of the alignment mark so that the density of trenches in the first exposure shot with the alignment mark and other second exposure shots are almost identical. Thus, a uniform polishing rate is provided in subsequent chemical-mechanical polishing operation.
Furthermore, whether the alignment mark is in the middle of the chip or on one side close to a die, one exposure is all that is required to form the dummy isolation region pattern around the alignment mark. Consequently, the alignment mark can be positioned in the middle of a die so that the effect of the alignment mark on the peripheral chips is greatly reduced.
Accordingly, the present invention provides a faster exposure process, decreases the fabrication cost, and providing a uniform polishing rate during chemical mechanical polishing. In addition, in the present invention the alignment mark can be positioned in the middle of a die so that the effect of the alignment mark on the peripheral chips is greatly reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.